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Similar Jobs SoC Design Engineer - Layout Verification

  • Bengaluru (Bangalore Urban)
  • Design / Civil engineering / Industrial engineering

Job description

Job Description

Responsibilities :-Full chip layout verification activities DRC/LVS on 10nm NCS designs, Setting up the environment for Full chip layout verification, Interacting with partition owners on LV Closure, Interacting with cross site teams on BKMs and methodology improvements

Inside this Business Group

The Platform Engineering Group (PEG) is responsible for the design, development, and production of system-on-a-chip (SoC) products that go into Intel's next generation client and mobile platforms. PEG strives to lead the industry moving forward through product innovation and world class engineering.

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Desired profile

Qualifications

Qualifications :BE/BTech in EC/EE with 4+ years, MTech. in EC/EE with 3+ years Experience :- Hands on experience on full chip layout verification activities on lower technology nodes - 14nm/10nm, Should have good exposure to ICV/Calibre, Should be able to debug LV decks,Should be conversant on ICC2, Working knowledge of PD flow and scripting in Tcl/Perl/Skill, Exposure to Intel flows would be additional advantage.

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