Senior Digital Design Engineer (f/m)

Job description

Job Description

You have a unique way of looking at the world. We want to see it.

Step inside our world and you'll find one brilliant mind after another working together in a spirit of collaboration that is simply contagious. And through this shared dedication-this culture of innovation and exploration-we do more than deliver the latest technologies. We deliver the future. See for yourself. Look Inside.

We invite you to join our creative and flexible Hardware Development team as Senior Design Engineer in Munich. As a member of the innovative worldwide Intel Communication and Devices Group (iCDG) you will work with leading-edge IPs and Technologies to revolutionize Mobile Computing.

As a Senior Design Engineer you will be a part of a talented and highly committed team of engineers that develops, maintain and support complex digital components for wireless basebands applications. You will be responsible for architecting, implementing and supporting of complex digital designs for wireless basebands applications throughout the entire chip development process.

Key aspects of this assignment are:

·  DSP Subsystem architecture & design in accordance to leading edge frequency, area & power requirements
·  Coverage-driven functional verification on all levels
·  Implementation of DfT structures
·  Constraining, logic synthesis and STA
·  Design automation, delivery & support during SOC integration & silicon bring-up
·  Interface to external and internal IP providers

Inside this Business Group

Intel is one of the largest suppliers of chips for the communications market. The Intel Communications group is focused on designing and building communications technologies such as Ethernet connectivity products, optical components, communications processing solutions and broadband products.

Desired profile

Qualifications

Required Qualifications

·  You should hold a Bachelor/Master's degree and/or a Ph.D. in Engineering, Computer Science, Mathematics or related field
·  At least 3 years of experience in digital design, architecture exploration, modelling, bring-up and methodology leadership
·  Strong expertise in Architecture and Design of complex DSP subsystems
·  Expertise in coverage-driven constraint-random functional verification

Optional Qualifications

·  Experience in design automation
·  Verification of highly configurable designs
·  Formal methods on specification and/or RTL implementation level
·  System Verilog Assertions (SVA), TLM 2.0 LT and AT, UPF, Tc,l, E, Java, Perl, SystemC
·  Specman, Synopsys VCS, Jasper Gold, Verdi/Debussy

Required Soft Skills

·  High motivation to learn leading edge technologies
·  Strong communication skills orally and in writing
·  Strong commitment to cross-functional, geographically dispersed teamwork
·  Willingness to take initiative and leadership